Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reduction in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, these activities involve communication of information and data between components and how the information is communicated can impact performance.
There are various traditional communication or interconnection topologies utilized to communicate information (e.g., basic tree, fat-tree, CLOS, 2D or 3D torus, etc.). There are also various protocols used in implementing the topologies (e.g., Peripheral Component Interconnect (PCI), PCI-Express (PCIe), etc.). Some of these protocols may be implemented in relatively simple communication environments or networks. PCIe is one of the most widely used interconnection mechanisms between central processing units (CPUs) and their immediate peripherals. These CPUs and immediate peripherals are typically deployed primarily at a printed circuit board (PCB) level within a single device or enclosure (e.g., a single PC, single server, etc.) and PCIe technology was originally designed as an onboard interconnection technology. Conventional PCIe environments or networks typically have only a single PCIe switch and a relatively few number of nodes (e.g., CPUs and I/O devices). In these limited and confined applications, some conventional PCIe approaches attempt to be a high throughput, low-latency, packet based and switched interconnection technology. However, as a practical matter, the types and complexity of topologies that can be implemented with conventional PCIe approaches are essentially limited (e.g., a small basic tree topology with relatively few levels and end-points, etc).
As the size and complexity of a network increases (e.g., the number of end-points and paths interconnected by the network increases, etc.), conventional basic tree topology and PCI type protocol attempts typically become inefficient and impractical. Traditional basic tree topology and PCI type protocol restrictions typically have constraints that restrict communication operations and path options (e.g., prohibit alternate paths or multiple communication paths between components, etc.) that have adverse impacts in some situations (e.g., the communication paths can become very long with lots of hops, etc.).
FIG. 1 is a block diagram of one example of a conventional attempt at a basic tree topology. As indicated in FIG. 1, there is a single communication path between switch 115 and switch 127 with relatively numerous multiple intervening hops (e.g., to switches 121, 122, 124, etc.) that communications must traverse. As also indicated in FIG. 1, there is a single communication path between end-point 181 and end-point 191 again with numerous multiple intervening hops (e.g., to switches 129, 128, 121, 115, 131, 133, etc.) that communications must traverse. As a practical matter, paths between switches and end-points become too long (e.g., in terms of hops, etc.) and components (e.g., links close to the root, etc.) become overloaded.
Some traditional approaches to network engineering attempt to use other topologies (e.g., fat-tree, CLOS, 2D or 3D torus, etc.). However, there is significant challenges to attempt to build such topologies with the conventional PCIe compatible technology due to the PCIe constraints associated with a basic tree topology and its inability to handle alternate connections.